Command control logic to complete the instruction fetch, instruction and execution analysis instruction. Timing control logic to provide necessary control signals for each instruction in chronological order. General clock timing signal is the most basic, is the time base of the entire machine, called the machine speeds. The time required to execute an instruction called an instruction cycle, different instruction cycles may be different. Is generally easy to control, according to the nature of the operation and control of the different nature of the instruction, the instruction cycle will be divided into several stages, each stage is a CPU cycle. Early
cpu modules memory with little difference in speed, so the
plc cpu cycles and memory access cycle is generally the same, and later, with the development of CPU speed has now a lot faster than memory, CPU cycles so often defined as memory access a fraction of the cycle.
Bus control logic circuit is a plurality of features and services for information passage. Generally divided on the CPU in terms of the internal bus and CPU external bus outreach, the external bus is sometimes also called the system bus, the front side bus (FSB) and so on.
An interrupt is a computer due to an abnormal event, or some event occurs randomly require immediate treatment, cause the CPU to suspend execution of the program now, switch to another service program to deal with this incident, processed and then return to the original program process. Interrupts generated by the internal machine, we call it a trap (internal interrupt), caused by an external device interrupts called external interrupts.
